The present invention relates to the organization and operation of a data processor, especially as relates to the transfer of image data between a first memory, such as a memory local to a data processor and another memory.
A large amount of data is typically required to be transferred for processing from a memory to a processor to produce high-quality images for display, particularly video images at display rates and resolutions equaling or exceeding that of standard television receivers, videotape recorders (VTRs), digital video disc (DVD) players, and the like.
In recent years, digital video compression standards such as the standard adopted by the International Organization for Standards (ISO), commonly referred to as MPEG-2 (Motion Picture Experts Group), have been developed to reduce the amount of data needed to display images of acceptable quality including video images.
However, despite the reduced amount of data needed to be transferred from memory to a processor, certain problems still exist which cause image data transfer operations to be inefficient and potentially cause bottlenecks affecting image processing performance.
A particular challenge for increasing the performance of an image processing system is to reduce the amount of overhead to transfer data for processing an image by way of a direct memory access controller (DMAC). A DMAC typically has hardware designed to handle transfers of data of a predetermined minimum size over a bus between a main memory and a local memory, such minimum size being known as “the hardware transfer size.” Such operation is generally well-adapted for the transfer of portions of an instruction stream and associated data from a main memory to a local memory of a processor, because the instructions in an instruction stream generally occupy contiguous areas of memory, as do the associated data. Thus, instructions and/or associated data can be transferred in units of the hardware transfer size of the DMAC.
However, that is not the case with image data. In the case of image data, data to be processed such as MPEG-2 data, is frequently arranged in a way that it is not easily transferred between a main memory and another memory in units of the hardware transfer size of the DMAC. The data may be arranged in memory in form of many lines of memory, so as to require fetching and storing of the lines of data on a line-by-line basis. This leads to at least two problems. One problem is that the DMAC must conduct a large number of operations to transfer all the lines of data from the one memory to another. A DMAC is typically designed to handle a finite number of data transfer operations at once. A large number of requests for transferring data received at one time, e.g., from a processor, could exceed the capabilities of the DMAC, and cause the DMAC to refuse the request. This in turn, could cause the processor issuing the request to be stalled until the transfer requests are accepted. Another problem is that a line of memory is generally smaller than the hardware transfer size of the DMAC. For example, in one system, a line of image data has 16 bytes of memory, while the hardware transfer size is 128 bytes. In such case, a large percentage (87.5%) of the data being transferred by one transfer operation (128 bytes) is discarded, because only the 16 bytes included in the line of memory are useful. Thus, under these conditions, the system is said to have a “bus efficiency” of 12.5%.
Accordingly, it would be desirable to provide a system and method of transferring data is desired which reduces a number of transfer operations performed by a direct memory access controller (DMAC) for transferring image data and which increases bus efficiency for transferring image data to a much higher level than before.